An Improved Bpsk Demodulator for the 1.2mbit/s Packet-radio Rtx ===============================================================

Efficient data transmission requires efficient modulation and demodulation techniques, both for terrestrial radio links and for satellite communications. Unfortunately, most amateur transmissions still use rather inefficient FSK modulation. Although an incoherent FM transceiver may look simpler than a coherent PSK transceiver, the practical implementation of either design is equally demanding. Coherent PSK becomes really necessary at data rates above about 100kbit/s, where the power and spectral inefficiency of incoherent FSK severely limits the performance even for short-range terrestrial links. The simplest form of coherent PSK is Biphase-PSK or BPSK. The latter is very suitable for amateur packet-radio links. Coherent BPSK was successfully tested already a few years ago in 1.2Mbit/s packet-radio links as described in [1]. The only disadvantage were relatively complicated 13cm BPSK transceivers, as described in [3] or [5]. In fact only the double-conversion 13cm BPSK receiver is complicated and requires lots of shielding and a complicated tuning procedure. On the other hand, it is always possible to design a direct-modulation BPSK transmitter without any frequency conversions or other complicated signal processing. The receiver radio-frequency hardware can be much simplified using a Zero-IF design as shown on figure 1. On the other hand, a Zero-IF receiver requires more complex IF signal processing. Since the latter is performed at relatively low frequencies, it only requires simple and inexpensive hardware. BPSK or QPSK demodulation simply requires an additional phasor rotation to compensate for the frequency and phase offset of the receiver local oscillator. A very successful 23cm Zero-IF BPSK transceiver design for 1.2Mbit/s was presented in [2], [4], [6] or [7]. This transceiver uses a Costas-loop BPSK demodulator. The phasor rotation is achieved with a pair of rotating, analog CMOS switches, while the feedback loop is built as a digital PLL, as shown on figure 2. This design results in inexpensive and highly reproducible hardware with no tuning points. The measured bit-error rate performance of the described demodulator is compared to the theoretical performance of a BPSK demodulator on figure 3. The performance loss amounts to about 3...4dB and has many sources. About 0.7dB loss is caused by rotating the phasor in 16 discrete steps instead of a continuous phase adjustment. Less-than-ideal IF filtering accounts for at least 1dB of performance loss. Additional performance loss is caused by the switching transients caused by the analog CMOS switches and the